Suvadeep Banerjee received his Bachelor's degree in Electrical Engineering from Jadavpur University, India in 2011 and Masters in Electrical and Computer Engineering from Georgia Institute of Technology in 2014. Presently he is working as a graduate research assistant in LARS Lab. His research focus lies in the development of error-resilient methodologies for reliability in digital and analog systems. His present research objective is to analyze and design energy-efficient and self-healing CN-TFT circuits which will consider statistical and morphological fluctuations and self-heating effects in those transistors. In the past he has worked on design of fault-tolerant analog circuits and error checking of linear control systems. Professionally, he has interned in Intel, Santa Clara where he investigated the problem of automated generation of test stimuli for analog circuits used in high-speed I/O systems.