Serious new technical challenges are barriers to advances in microelectronics technology as technology scaling comes up against fundamental limits of material properties and lithography. Large process variations and other random performance and power constraining imperfections are now being observed as microelectronic devices are scaled down to atomic dimensions. This requires that module level performance in electronic designs be pessimistically guardbanded to ensure proper overall system level functionality, forcing systems to operate at performance levels far below the inherent capability of the underlying design fabric. In addition, embedded DSP systems must be designed to work under worst case operating conditions resulting from ill-conditioned input signals. Wider guardbands from increasing performance and input signal variability in future technologies can negate most of the performance benefits of scaling, stalling a key payoff from Moore?s Law for embedded systems. In such an environment, introduction of new scaled devices will be cost-effective only if the guardbands can be controlled down to acceptable margins, despite the presence of these uncertainties. This remains a major unsolved challenge, especially for embedded DSP processors that must be concurrently optimized for system level power, performance and reliability. To address these problems, this project is developing the concept of test, diagnosis and continuous signal monitoring enabled dynamic circuit-architecture-algorithm co-modulation (or co-tuning) for both static (procees) and dynamic (input signal) uncertainties. Under this new design paradigm, feedback driven reconfiguration control mechanisms involving circuitry and software (?tuning knobs?) are designed into the IC to support power-performance trade-off and reliability recovery post manufacture. The research pursues vertically integrated circuit-architecture-algorithm tuning methods that offer 10X benefits over optimizations performed at a single level of the design hierarchy. The diagnostic information generated is used to dynamically optimize (post-manufacture) individual module level behavior to optimize system level performance, power and reliability metrics via specially designed hardware and software control mechanisms. In this way, each instantiation of a design adapts to the maximum performance, power, and reliability levels it is capable of in the presence of process variations and adverse operating conditions. Graduate students working on the project receive a unique kind of training in this multidisciplinary research, which together the fields of digital design and test, control systems, embedded digital signal processing architectures, and algorithms. The students participate in summer internship programs with industry. Through joint efforts at Georgia Tech, Auburn University, and Tuskegee University, this project also actively supports the goals of recruiting more U.S. citizens, women and minorities to graduate programs.
This material is based upon work supported by the National Science Foundation under Grant No. CCR-0834484