Students

Current Students

Suvadeep Banerjee

Suvadeep Banerjee received his Bachelor's degree in Electrical Engineering from Jadavpur University, India in 2011 and Masters in Electrical and Computer Engineering from Georgia Institute of Technology in 2014. Presently he is working as a graduate research assistant in LARS Lab. His research focus lies in the development of error-resilient methodologies for reliability in digital and analog systems. His present research objective is to analyze and design energy-efficient and self-healing CN-TFT circuits which will consider statistical and morphological fluctuations and self-heating effects in those transistors. In the past he has worked on design of fault-tolerant analog circuits and error checking of linear control systems. Professionally, he has interned in Intel, Santa Clara where he investigated the problem of automated generation of test stimuli for analog circuits used in high-speed I/O systems.

Md Imran Momtaz

Md received his bachelors degree in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) in December 2009 and he joined Professor Chatterjee's group at January, 2015. Before starting joning this group Md searved in BUET as instructor for 4 years. His Research interests include low overhead methodology for detection, diagnosis, and correction of electronic and mechanical systems. During his PhD program, he interned in Texas Instruments and Intel. In broad sense, his responsibilities include testing of autonomous system for safety.

Alumni

Jayaram Natarajan

Jayaram Natarajan was born and raised in Mumbai, India. He received his Bachelors Degree in Electronics Engineering from University of Mumbai. After working for a couple of years as a Software Developer, he moved to Atlanta, GA to attend graduate school at Georgia Tech. He received his Masters Degree in Electrical and Computer Engineering in 2009 and is currently a PhD student. His areas of interest spans across power and performance efficient micro-architecture designs, reliable computing and parallel algorithms. During his PhD studies, he has held internship and full-time positions at Intel and Qualcomm. He enjoys backpacking, travel, biking, soccer and Barcelona

Joshua W. Wells

Josh Wells received his bachelors degree in Computer Engineering from University of North Carolina at Charlotte in 2008. His Research interests include Low Power Adaptive Algorithms, Digital Signal Processing and Computer Engineering. He is currently working in content-aware low-power video encoding techniques for developing new algorithm and hardware based techniques for power-efficient computing with graceful degradation of quality.

Debashis Banerjee

Debashis received his B.E. degree in Electronics & Tele-comm engineering from Jadavpur University, kolkata, India in 2007, his masters (M.Tech.) in 2010 from Indian Institute of Technology, Kharagpur (IIT-KgP) specializing in Microelectronics & VLSI Design. He also received his M.S. degree in Electrical and Computer Engg. from Georgia Tech in 2013. His research interest is in channel adaptive process resilient communication system and circuit design. In the past, he has worked at Magma Design Automation, Bangalore and has interned at Qualcomm Research & Kilby Labs (Texas Instruments) in the summers of 2012 and 2013 respectively. He is a Ph.D. student in LARS lab and is also working as Senior Analog and Mixed-signal Design Engineer at Marvell Semiconductor, Austin. 

Thomas Moon

Thomas Moon received the B.S. degree in electrical electronic engineering from Pohang University of Science and Technology (POSTECH), Pohang, Korea, in 2008, and the M.S. degree in electrical and computer engineering from Georgia Institute of Technology, Atlanta, in 2012, where he is currently pursuing the Ph.D. degree. He is currently working as a Graduate Research Assistant with LARS lab, Georgia Institute of Technology. His current research interests include high-speed signal testing and characterization, signal integrity, and signal reconstruction by undersampling algorithm.